For those with the pressure heaped on by yields crashing and deliveries being missed there are few better feelings than finding a proof of the root cause of yield loss. Having helped another customer do exactly that this week I share in that elated feeling and want to write about it!
Semiconductor manufacturing is extremely complex and the methods used result in processes that do not give 100% yield. This means that semiconductor yield management is necessary at all levels of the industry. From consumer products where the price demands that every fraction of a cent in scrap needs to be saved, to high reliability where an individual unit on a satellite in orbit must operate for tens of years, yield is crucially important to long-term success.
So to the root cause! I recommend the following flow to find the root cause.
- Check long-term trends, yield across as much data as you have available, preferably at least one year of data.
- Pareto highest failing bins and highest failing tests, over thousands, or ten of thousands of wafers if you have that much data.
- Choose one yield issue to focus on, usually the highest failing test or highest failing bin. Select data only from wafers that have yield loss for this issue. For example >5% yield loss on bin15.
- Stack wafer maps from all of these wafers, more than 100 wafers will show how consistent failure patterns are. The root cause may already start to become clear from the failure pattern.
- The next analysis depends on the results of step 4, it could be that the fail pattern appears to be stepper field related in which case use reticle analysis. In the recent cases I supported customers on the next step has been carry out genealogy correlation.
- In one case the failing test was digital so failure rate at probe / wafer sort is correlated against Fab WAT /E-Test data. In the next case the failing test was analog and failing as the high side of the distribution crosses the upper limit, in this case we correlated the max value after a robust data filter was applied.
- Root Cause! The charts are shown below for each case, in the first case the process structure used in the design is unstable as the breakdown voltage is low but still within spec. In the second case the product only has high yield if the sheet resistance is central or high! Usually low sheet resistance would be desirable but not in this design!
An expected question at this stage is “How long does that take!” the answer is about 2-3 hours. There is no need for it to take longer. This is one of the benefits of data management using a leading yield management system.
The really exciting thing about doing this kind of in depth root cause analysis is that it can now be done so efficiently even using big data. The methods are equally applicable for fabless semiconductor companies, IDM (Integrated Design and Manufacture) as well as foundry companies offering turnkey solutions.
Finding the root cause of our customer’s yield issues using genealogy correlation is just one of the things we do at MFG Vision. You can find out more on our website www.mfgvision.com or contact me…
Kevin Robinson, Director of Sales & Marketing at MFG Vision (still practicing semiconductor engineer)